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ISL54062
Data Sheet February 25, 2009 FN6581.0
+1.8V to +6.5V, Sub-Ohm, Dual SPDT Analog Switch with Negative Signal Capability and Click and Pop Elimination
The Intersil ISL54062 device is a low ON-resistance, low voltage, bidirectional, dual single-pole/double-throw (SPDT) analog switch. It is designed to operate from a single +1.8V to +6.5V supply and pass signals that swing up to 6.5V below the positive supply rail. Targeted applications include battery powered equipment that benefit from low rON (0.56), low power consumption (20nA) and fast switching speeds (tON = 55ns, tOFF = 18ns). The digital inputs are1.8V logic-compatible up to a +3V supply. The ISL54062 also features integrated circuitry to eliminate click and pop noise to an audio speaker. The ISL54062 is offered in a small form factor package, alleviating board space limitations. It is available in a tiny 10 Ld 1.8x1.4mm TQFN or 10 Ld 3x3mm TDFN package. The ISL54062 is a committed dual single-pole/double-throw (SPDT) that consist of two normally open (NO) and two normally closed (NC) switches with independent logic control. This configuration can be used as a dual 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE ISL54062 Number of Switches SW 4.3V rON 4.3V tON/tOFF 2.7V rON 2.7V tON/tOFF 1.8V rON 1.8V tON/tOFF Packages 2 SPDT or 2-to-1 MUX 0.57 43ns/23ns 0.82 55ns/18ns 1.8 145ns/28ns 10 Ld TQFN, 10 Ld TDFN
Features
* Pb-free (RoHS Compliant) * Negative Signal Capability * Audio Click and Pop Elimination Circuitry * ON-Resistance (rON) - V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.57 - V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.82 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 * rON Matching Between Channels . . . . . . . . . . . . . . . . . 10m * rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.35 * Low THD+N @ 32 Load . . . . . . . . . . . . . . . . . . . . . . .0.02% * Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . 20nA * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV * Guaranteed Break-before-Make * 1.8V Logic Compatible (+3V supply) * Low I+ Current when VINH is not at the V+ Rail * Available in 10 Ld TQFN 1.8x1.4mm and 10 Ld 3x3mm TDFN
Applications
* Audio and Video Switching * Battery powered, Handheld, and Portable Equipment - MP3 and Multimedia Players - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54062 Pinout
(Note 1) ISL54062 (10 LD TDFN) TOP VIEW
IN1 1 NO1 2 COM1 3 NC1 4 GND 5 CLICK AND POP CIRCUITRY 10 IN2 9 NO2 8 COM2 7 NC2 6 V+
Truth Table
IN1 0 0 1 1 NOTE: IN2 0 1 0 1 NC1 ON ON OFF OFF NO1 OFF OFF ON ON NC2 ON OFF ON OFF NO2 OFF ON OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Pin Descriptions
PIN V+ FUNCTION IC Power Supply (+1.8V to +6.5V). Decouple V+ to ground by placing a 0.1F capacitor at the V+ and GND supply lines as near as the IC as possible. Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
ISL54062 (10 LD TQFN) TOP VIEW
IN1 7 NO1 8 IN2 6 5 NO2
GND INx COMx NOx
COM1
9 CLICK AND POP CIRCUITRY 1 GND 2 V+
4
COM2
NCx
NC1
10
3
NC2
NOTE: 1. Switches Shown for INx = Logic "0".
Ordering Information
PART NUMBER ISL54062IRTZ (Note 3) ISL54062IRTZ-T (Notes 2, 3) ISL54062IRUZ-T (Notes 2, 4) NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4062 4062 8 PART MARKING TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN (Tape and Reel) 10 Ld Thin TQFN (Tape and Reel) PACKAGE (Pb-Free) PKG. DWG. # L10.3x3A L10.3x3A L10.1.8x1.4A
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FN6581.0 February 25, 2009
ISL54062
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltages NOx, NCx (Note 5) . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COMx (Note 5) . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) Continuous Current NOx, NCx, or COMx. . . . . . . . . . . . . 300mA Peak Current NOx, NCx, or COMx (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld 3x3 TDFN Package (Notes 6, 8) 55 18 10 Ld TQFN Package (Note 7) . . . . . 155 N/A Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . (V+ - 6.5)V to V+
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 5. Signals on NC, NO, IN, or COM exceeding V+ or GND by specified amount are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless
Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON rON Matching Between Channels, rON rON Flatness, RFLAT(ON) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1) 25 Full 25 Full Full 25 25 25 25 25 25 35 50 16 22 18 170 60 -75 0.02 60 36 ns ns ns ns ns pC dB dB % MHz pF V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5) to V+ (see Figure 5) V+ = 4.5V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 13) V+ = 4.5V, ICOM = 100mA, VNO or VNC = (V+ - 6.5) to V+, (Note 12) V+ = 5V, VCOM = -1.5V, 5V, VNO or VNC = Float 25 Full 25 Full 25 Full 25 Full 0.55 0.68 15 30 0.11 0.14 49 0.7 m m nA A TEST CONDITIONS TEMP MIN (C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS
Break-Before-Make Time Delay, tD V+ = 5.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 3) Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion -3dB Bandwidth NO x or NCx OFF Capacitance, COFF VG = 0V, RG = 0, CL = 1.0nF (see Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32 VCOM = 1VRMS, RL = 50, CL = 5pF f = 1MHz
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FN6581.0 February 25, 2009
ISL54062
Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 9), Unless
Otherwise Specified. (Continued) PARAMETER COMx ON Capacitance, CCOM(ON) Positive Supply Current, I+ TEST CONDITIONS f = 1MHz (see Figure 7) TEMP MIN (C) (Notes 10, 11) 25 TYP 88 MAX (Notes 10, 11) UNITS pF
POWER SUPPLY CHARACTERISTICS V+ = 5.5V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full Full 25 Full 2.4 -0.1 0.89 0.8 0.1 V V A A 0.02 2.5 0.1 A A
Electrical Specifications - 4.3V SupplyTest Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless
Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (See Figure 5) V+ = 4.3V, ICOM = 100mA, VNO or VNC = Voltage at max rON, (Note 12) V+ = 4.3V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (Note 13) V+ = 4.3V, VCOM = -1.2V, 4.3V, VNO or VNC = Float 25 Full 25 Full 25 Full 25 Full -0.1 0.57 0.68 15 30 0.1 0.14 1.1 0.1 m m A A TEST CONDITIONS TEMP MIN (C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS
rON Matching Between Channels, rON rON Flatness, RFLAT(ON)
COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (see Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (see Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4)
25 Full 25 Full Full 25 25 25 25 25 25
-
43 50 23 23 22 200 60 -75 0.04 36 88
-
ns ns ns ns ns pC dB dB % pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF-Isolation
Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) Total Harmonic Distortion NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 f = 1MHz f = 1MHz (see Figure 7)
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FN6581.0 February 25, 2009
ISL54062
Electrical Specifications - 4.3V SupplyTest Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 9), Unless
Otherwise Specified. (Continued) PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 0.003 2.6 0.89 0.1 12 A A A TEST CONDITIONS TEMP MIN (C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Full Full 25 Full 1.6 -0.5 0.5 0.5 0.5 V V A A
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 9), Unless
Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (see Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 13) V+ = 2.7V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (Notes 12, 14) 25 Full 25 Full 25 Full 0.82 0.94 10 30 0.35 0.4 0.5 0.55 m m TEST CONDITIONS TEMP MIN MAX (C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
rON Matching Between Channels, rON rON Flatness, RFLAT(ON)
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 1) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (see Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (see Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (see Figure 4) RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS (see Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 32 f = 1MHz f = 1MHz (see Figure 7) 25 Full 25 Full Full 25 25 25 25 25 25 55 82 18 24 30 150 60 -75 0.04 36 88 ns ns ns ns ns pC dB dB % pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ 25 25 25 Full 1.4 -0.5 0.4 0.5 0.5 V V A A
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FN6581.0 February 25, 2009
ISL54062
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 9), Unless Otherwise
Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+, (see Figure 5) V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 13) V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V) to V+ (Note 12) 25 Full 25 Full 25 Full 1.87 1.97 16 30 1.34 1.43 m m TEST CONDITIONS TEMP (C) MIN (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS
rON Matching Between Channels, rON rON Flatness, RFLAT(ON)
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF (see Figure 1) V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF (see Figure 1) 25 Full 25 Full Full 25 25 25 25 145 150 20 22 130 40 60 36 88 ns ns ns ns ns pC MHz pF pF
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, V+ = 1.8V, VNO or VNC = 1.8V, RL = 50, CL = 35pF tD (see Figure 3) Charge Injection, Q -3dB Bandwidth NOx or NCx OFF Capacitance, COFF COMx ON Capacitance, CCOM(ON) CL = 1.0nF, VG = 0V, RG = 0 (see Figure 2) VCOM = 1VRMS, RL = 50, CL = 5pF f = 1MHz f = 1MHz (see Figure 7)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL Input Current, IINH, IINL NOTES: 9. VIN = input voltage to perform proper function. 10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2 or between NO1 and NO2. 14. Limits established by characterization and are not production tested. V+ = 2.0V, VIN = 0V or V+ V+ = 2.0V, VIN = 0V or V+ 25 25 25 Full 1.0 -0.5 0.38 0.4 0.5 V V A A
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FN6581.0 February 25, 2009
ISL54062 Test Circuits and Waveforms
V+ V+ LOGIC INPUT 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% LOGIC INPUT SWITCH INPUT NO OR NC COM IN GND RL 50 CL 35pF VOUT 50% tr < 5ns tf < 5ns C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) ----------------------R L + r ON FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
RG SWITCH OUTPUT VOUT VOUT VG V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON
NO OR NC
COM
VOUT
GND
IN
CL LOGIC INPUT
Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V VNX
NO COM NC IN RL 50 GND
VOUT CL 35pF
SWITCH OUTPUT VOUT
90% 0V tBBM
LOGIC INPUT
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
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FN6581.0 February 25, 2009
ISL54062 Test Circuits and Waveforms (Continued)
V+ C *50 SOURCE SIGNAL GENERATOR V+ C NO OR NC rON = V1/100mA NO OR NC IN 0V OR V+ VNX 100mA ANALYZER RL COM GND COM GND V1 IN 0V OR V+
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 4. OFF-ISOLATION TEST CIRCUIT
Repeat test for all switches. FIGURE 5. rON TEST CIRCUIT
V+ C *50 SOURCE SIGNAL GENERATOR
V+ C
NO1 OR NC1
COM1
50
COM
INX 0V OR V+ IMPEDANCE ANALYZER
IN
0V OR V+
ANALYZER RL
COM2
NC2 OR NO2 NC GND
NO OR NC
GND
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. ON CAPACITANCE TEST CIRCUIT
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FN6581.0 February 25, 2009
ISL54062 Test Circuits and Waveforms (Continued)
INx VDC 0V VINx* 0V tD tD VDC CLICK AND POP CIRCUITRY 220uF NOx tD = 200ms measured at 50% points. VDC COMx 220uF NCx
*VINx waveform for Click and Pop Elimination on NOx terminal.
For Click and Pop Elimination on NCx terminal invert VINx.
RL
FIGURE 8A. CLICK AND POP WAVEFORM FIGURE 8B. CLICK AND POP TEST CIRCUIT FIGURE 8. CLICK AND POP ELIMINATION
Detailed Description
The ISL54062 is a bi-directional, dual single pole-double throw (SPDT) analog switch that offers precise switching from a single 1.8V to 6.5V supply with low ON-resistance (0.83), high speed operation (tON = 55ns, tOFF = 18ns) and negative signal swing capability. The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (20nA @ 3V), and a tiny 1.8mmx1.4mm TQFN package or a 3x3 TDFN package. The low ON-resistance and rON flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch.
the input current below the threshold that produces permanent damage. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Alternatively, connecting external Schottky diodes from the V+ rail to the signal pins will shunt the fault current through the Schottky diode instead of through the internal ESD diodes, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current.
V+ +RING
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. The ISL54062 contains ESD protection diodes on each pin of the IC (see Figure 9). These diodes connect to either a +Ring or -Ring for ESD protection. To prevent forward biasing the ESD diodes to the +Ring, V+ must be applied before any input signals, and the input signal voltages must remain between recommended operating range. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 9). The resistor limits
VCOMx
VNCx VNOx CLAMP
1k LOGIC INPUTS
GND -RING
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54062 construction is typical of most single supply CMOS analog switches which have two supply pins: V+ and GND. V+ and GND provide the CMOS switch bias and sets their analog voltage limits. Unlike switches with a 5.5V maximum supply voltage, the ISL54062's 6.5V maximum supply voltage provides plenty of head room for the 10% tolerance of 5.5V supplies due to overshoot and noise spikes.
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FN6581.0 February 25, 2009
ISL54062
The minimum recommended supply voltage is 1.8V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables, beginning on page 3, and "Typical Performance Curves", beginning on page 11, for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to V+ and GND signals levels to drive the analog switch gate terminals. A high frequency decoupling capacitor placed as close to the V+ and GND pin as possible is recommended for proper operation of the switch. A value of 0.1F is highly recommended. placed on the COM pin. This impedance is small enough to reduce the voltage build up significantly while not increasing the power dissipation dramatically. Current consumption considerations will need to be taken for driving a smaller load impedance under this scenario.
V+ AUDIO SOURCE A 220F
NO
C
RSH
COM RL 32
Negative Signal Capability
The ISL54062 contains circuitry that allows the analog input signal to swing below ground. The device has an analog signal range of 6.5V below V+ up to the V+ rail (see Figure 16) while maintaining low rON performance. For example, if V+ = 5V, then the analog input signal range is from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V to +2.7V.
220F AUDIO SOURCE B IN
NC
RSH
GND
ISL54062
Click and Pop Operation
The ISL54062 contains circuitry that prevents audible click and pop noises that may occur when audio sources are powered on or off. Single supply audio sources are biased at a DC offset that can generate transients during power on/off. A DC blocking capacitor is needed to remove the DC bias at the speaker load. For 32 headphones, a 220F capacitor is typically used to preserve the audio bandwidth. The power on/off transients are AC coupled by the 220F capacitor to the speaker load causing a click and pop noise. The ISL54062 has shunt switches on the NO and NC pins to eliminate click and pop transients (see Figure 10). These switches are driven complimentary to the main switch. When NC is connected to COM, the shunt switch is active on the NO pin (and vice versa). The shunt switches connect an impedance (140 typical, see Figure 24) from the NO/NC pin to ground to discharge any transients that may appear on the NO or NC pins. When a DC bias becomes active at the source, the NO and NC terminals will also have a DC offset due to capacitor dv/dt principle. The DC offset will be discharged through the shunt impedance on the NO and NC terminals instead of the speaker, eliminating click and pop noise. *Under high impedance loads such as the input impedance of pre-amplifiers (20k), the COM terminal voltage may rise due to small leakage currents charging the COM capacitance. This is not seen when low impedance loads such as headphones (32) are used because the small leakage currents does not result in significant potential drop across the load. If the user desires to reduce the voltage build up on the COM pin, a 1k resistor to ground may be
FIGURE 10. CLICK AND POP OPERATION
Click and Pop Elimination with INx Pin
Audio click and pop elimination can be driven with the Input Select (INx) pin. When INx = 0, the NOx terminals are connected to the shunt impedance. When INx = 1, the NCx terminals are connected to the shunt impedance. In this situation, only one of the source transient voltages will be shunted to ground, depending on the Input Select state. The Input Select pin should be driven 200ms after any source transients occurs to prevent audible transients at the speaker load.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.45V VOLMAX and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V (see Figure 18). At 3.3V the VIL level is 0.5V maximum. This is still below the 1.8V CMOS guaranteed low output maximum level of 0.45V, but noise margin is reduced to approximately 50mV. At 3.3V the VIH level is 1.4V minimum. While this is above the 1.8V CMOS guaranteed high output minimum of 1.35V, under most operating conditions the switch will recognize this as a valid logic high. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54062 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 2.85V logic high while operating with a 4.2V supply the device draws only 1A of current.
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ISL54062
High-Frequency Performance
In 50 systems, the ISL54062 has an ON switch -3dB bandwidth of 60MHz (see Figure 21). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor across the open terminals and AC couples higher frequencies, resulting in signal feed-through from a switch's input to its output. Off-Isolation is the resistance to this feed-through. Crosstalk indicates the amount of feed-through from one switch channel to another switch channel. Figure 22 details the high Off-Isolation and Crosstalk rejection provided by this part. At 100kHz, Off-Isolation is about 60dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. At 1MHz, Crosstalk is about -75dB in 50 systems, decreasing approximately 20dB per decade as frequency increases.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin, V+ and GND. One of these diodes conducts if any analog signal exceeds the recommended analog signal range. Virtually all the analog switch leakage current comes from the ESD diodes and reversed biased junctions in the switch cell. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased to either the +Ring or -Ring and the analog input signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the +Ring or -Ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current.
Typical Performance Curves TA = +25C, Unless Otherwise Specified
2.0 1.8 1.6 1.4 rON () 1.2 1.0 0.8 0.6 0.4 0.2 -6 V+ = 2.7V V+ = 4.5V rON () ICOM = 100mA V+ = 1.8V 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 -5 -4 -3 -2 -1 0 1 2 3 4 5 0.30 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 T = -40C T = +25C T = +85C V+ = 4.5V ICOM = 100mA
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
1.00 0.95 0.90 0.85 0.80 0.75 rON () rON () 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 T = -40C T = +25C T = +85C V+ = 4.3V ICOM = 100mA
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
1.25 1.15 1.05 0.95 0.85 0.75 0.65 0.55 0.45 0.35 -5 T = -40C -4 -3 -2 0 -1 VCOM (V) 1 2 3 4 T = +85C T = +25C V+ = 2.7V ICOM = 100mA
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
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ISL54062 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
2.2 V+ = 1.8V 2.0 1.8 1.6 1.4 rON () 1.2 1.0 0.8 0.6 0.4 T = -40C 0.2 6 -5 -4 -3 -2 -1 VCOM (V) 0 1 2 3 T = +85C T = +25C ICOM = 100mA ANALOG SIGNAL RANGE (V) 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 6.0 SIGNAL MIN SIGNAL MAX
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
700 650 600 550 500 450 Q (pC) 400 350 300 250 200 150 100 50 0 -5 -4 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 6 V+ = 2.0V V+ = 3.3V ABSOLUTE VALUES V+ = 5.5V
FIGURE 16. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE
1.6 1.5 1.4 1.3 1.2 VINH AND VINL (V)
V+ = 4.5V
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5
VINH
VINL
2.0
2.5
3.0 V+ (V)
3.5
4.0
4.5
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
160 T = -40C 140 120 100 tON (ns) tOFF (ns) 80 60 40 20 0 T = +25C T = +85C
40 T = -40C 35 30 25 20 15 10 5 0 1.8 3.3 V+ (V) 4.5 5.5 T = +25C T = +85C
1.8
3.3 V+ (V)
4.5
5.5
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
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ISL54062 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
0 V+ = 1.8V TO 5.5V -1 NORMALIZED GAIN (dB) -30 CROSSTALK (dB) -2 -3 -4 -5 -40 -50 -60 CROSSTALK -70 -80 -90 RL = 50 VIN = 1VRMS @ 0VDC OFFSET 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G -100 -110 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M OFF-ISOLATION -10 -20 V+ = 1.8V TO 5.5V RL = 50 VIN = 1VRMS @ 0VDC OFFSET
FIGURE 21. FREQUENCY RESPONSE
FIGURE 22. CROSSTALK AND OFF-ISOLATION
0.05
350 325 V+ = 1.8V
0.04
707mVRMS 360mVRMS
300 275 250 225 200 V+ = 3V V+ = 4.3V 150 125 100 75 50 V+ = 5V
THD+N (%)
0.03
0.02
177mVRMS
175
0.01
V+ = 3.3V VBIAS = 0VDC RL =32
0 20
100
200 1k 2k FREQUENCY (Hz)
10k
20k
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
SWITCH VOLTAGE (V)
FIGURE 23. TOTAL HARMONIC DISTORTION vs FREQUENCY
FIGURE 24. SHUNT RESISTANCE vs SWITCH VOLTAGE
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ISL54062 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
INx (1V/DIV) V+ = 3V VDC = 1.5VDC RL = 20k
V+ = 3V VDC = 1.5VDC RL = 32 VDC (1V/DIV) INx (1V/DIV)
VDC (1V/DIV)
VNO (500mV/DIV)
VNO (500mV/DIV)
*VCOM (10mV/DIV)
VCOM (10mV/DIV)
*See CLICK AND POP OPERATION TIME ( 200ms/DIV)
TIME ( 200ms/DIV)
FIGURE 25. CLICK AND POP ELIMINATION 20k LOAD 200ms DELAY
FIGURE 26. CLICK AND POP ELIMINATION 32 LOAD 200ms DELAY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (DFN Paddle Connection: Tie to GND or Float) TRANSISTOR COUNT: 432 PROCESS: Submicron CMOS
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ISL54062 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// A 0.10 C 0.08 C
0.20 2.95 2.25 2.95 1.45
0.25 3.0 2.30 3.0 1.50 0.50 BSC
0.30 3.05 2.35 3.05 1.55
5, 8 7, 8 7, 8 -
E2 e k
0.25 0.25
0.30 10 5
0.35
8 2 3 Rev. 3 3/06
C SEATING PLANE
SIDE VIEW
A3
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L1 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions.
FOR ODD TERMINAL/SIDE
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ISL54062 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.75 1.35 0.20 1.80 1.40 0.40 BSC 0.35 0.45 0.40 0.50 10 2 3 0 12 0.45 0.55 0.25 1.85 1.45 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions.
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
D
C
E e L L1 N
(DATUM A) PIN #1 ID L1 NX L 1 2 NX b 5 10X 0.10 M C A B 0.05 M C 5 7 e BOTTOM VIEW (DATUM B)
Nd Ne
NX (b) 5
(A1)
C L
L SECTION "C-C" CC 2.20 1.00 0.60 e TERMINAL TIP
9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
0.50 1.80 0.40 0.20 0.40 10 LAND PATTERN 0.20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6581.0 February 25, 2009

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